words per minute

A digital phase-shifting frequency-dividing clock has been designed with CPLD(Complex Programmable Logic Device) technique which modularizes hardware circuit and integrates different modules into one chip.

设计了一种数字移相分频钟 ,其中利用了先进的复杂可编程逻辑器件(CPLD -ComplexProgrammableLogicDevice)技术 ,将硬件电路模块化 ,把各功能模块集成在一个芯片中。